This invention relates to methods for producing application-specific integrated circuit (“ASIC”) equivalents of programmable logic devices such as field-programmable gate arrays (“FPGAs”).
The ASICs referred to herein are structured ASICs in the sense that they have a basic organization, structure, or architecture that is predetermined or fixed. Only certain features of the ASIC are customizable to meet each user's particular design. For example, many of the device-fabrication masks that are needed to make the ASIC are always at least substantially the same. Only some of the masks in the set are customized to implement a particular user's design. Examples of features that are always at least substantially the same may include the masks that produce the operational elements of the ASIC. Examples of features that may be customized include certain aspects of the circuitry that interconnects various operational elements. Use of ASICs that are basically structured in this way, and that therefore require only some masks to be customized, greatly simplifies and speeds up the process of producing ASIC equivalents of FPGAs. This approach also has numerous other advantages such as lower cost, lower risk of error, etc.
Chua et al. U.S. patent application Ser. No. 10/884,460, filed Jul. 2, 2004, (“the Chua reference”) discusses some examples of when it may be desirable to provide an ASIC equivalent of an FPGA. The Chua reference (which is hereby incorporated by reference in its entirety) shows ASIC architectures that are structured to facilitate providing FPGA equivalents. The Chua reference also shows methods for equivalently implementing a user's logic design in either an FPGA or a structured ASIC. Improvements, refinements, and enhancements in this general type of technology are always being sought, and the present invention provides various such improvements, refinements, and enhancements.